Typically, semiconductor devices are fabricated by depositing, etching and planarizing different material layers over one another.
In some deposition processes the deposition of a material layer may form an overhang along sidewalls and/or over the top surface of the material layer. There are several known methods to avoid or to remove undesired formations of overhangs prior to the deposition of subsequent material layers.
One known method avoids such overhangs by providing an additional semiconductor manufacturing step such as the application of tetra-ethyl-ortho-silicate (TEOS) spacers. Another known method removes unwanted materials under overhangs by an etch process which is less anisotropic and more isotropic. However, such an approach creates other disadvantages such as less control of line widths.